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| 基于FPGA的双边沿触发实现 |
| The Implementation of Double-edge-trigger Based on FPGA |
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| DOI：10.3969/j.issn.1671-5322.2012.01.011 |
| 中文关键词: 延时 单稳态触发器 采样 双边沿触发 FPGA |
| 英文关键词: delay monostable trigger sampling double-edge trigger FPGA |
| 基金项目: |
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| 摘要点击次数: 5113 |
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| 中文摘要: |
| 数字系统的时钟树走线最长,连接器件最多。单边沿触发的数字系统冗余的时钟边沿跳变必带来不容忽视的功率浪费。针对FPGA/CPLD中触发器均是单边沿触发的特点,用延时法、单稳态触发器法与采样法对时钟进行倍频处理,实现了系统的双边沿触发。在同样的时钟触发下,系统功耗大大降低,且系统数据处理速度提升一倍。 |
| 英文摘要: |
| Digital clock tree routing system is the longest,most connected devices.Redundant clock edge transition of single-edge triggered digital system will bring power waste that can not be ignored.For the characteristics,all triggers in FPGA/CPLD are single edge-triggered flip-flops,in this paper,by the delay method,monostable trigger method and the sampling method,to double clock frequency and achieve double-edge triggered system.With the same clock,the system power consumption is substantially reduced,and the system data processing speed is doubled. |
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