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| 基于HLS和PYNQ图像缩放的硬件加速器设计 |
| Design of Image Scaling Hardware Accelerator Based on HLS and PYNQ |
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| DOI：10.16018/j.cnki.cn32-1650/n.202302010 |
| 中文关键词: FPGA 缩放算法 HLS PYNQ Jupyter Lab |
| 英文关键词: FPGA scaling algorithm HLS PYNQ Jupyter Lab |
| 基金项目: |
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| 摘要点击次数: 35 |
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| 中文摘要: |
| 针对CPU进行图像处理已经无法满足系统实时性需求这一情况，提出了一种基于HLS和PYNQ的图像处理硬件加速器设计。该设计利用了FPGA具有数据并行处理的优势，克服了FPGA不易开发、移植性较差的缺陷。首先选择图像缩放处理算法作为实验的测试对象；然后在ZYNQ平台上根据软硬件协同的特点分配不同的系统任务，通过HLS开发工具使用C++实现和优化图像处理算法，并转化成RTL文件，再打包成IP核输出；在Vivado2018. 3上搭建硬件实验平台，通过Jupyter Lab对实验进行验证和分析。结果表明，缩放算法的处理速度由CPU端的 1 110 ms缩减为FPGA端的213 ms，执行速度提升了5倍。 |
| 英文摘要: |
| In view of the fact that image processing by CPU can no longer meet the real-time requirements of the system, a hardware accelerator design for image processing based on HLS and PYNQ is proposed. This design makes use of the advantages of data parallel processing of FPGA, and overcomes the defects of difficult development and poor portability of FPGA. First, the Image scaling processing algorithm is selected as the test object of the experiment. Then, different system tasks are assigned on ZYNQ platform according to the characteristics of software and hardware cooperation. The image processing algorithm is realized and optimized by using C++ through HLS development tools, which is converted into RTL files and then packaged into IP cores for output. A hardware experimental platform was built on Vivado2018. 3, and the experiment was verified and analyzed by Jupyter Lab. The results show that the processing speed of the scaling algorithm has been reduced from 1 110 ms on the CPU side to 213 ms on the FPGA side, and the execution speed is increased by 5 times. |
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