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| 单精度浮点数到十进制数转换的IP核设计 |
| IP Core Design of Single- precision Floating- point to Decimal Conversion |
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| DOI：10.3969/j.issn.1671-5322.2011.01.013 |
| 中文关键词: IEEE 754浮点数 十进制码 FPGA IP核 |
| 英文关键词: IEEE 754 floating-point BCD FPGA IP core |
| 基金项目: |
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| 中文摘要: |
| 采用FPGA进行数字信号处理的系统,总是要频繁的进行IEEE 754浮点数到十进制码的转换.设计针对FPGA的特点提出了一种以简单的移位和加减操作为核心的转换算法,并用VHDL语言编写了状态机结构的IP核.在EP1C6Q240C8芯片上实现了732个逻辑单元的使用以及69.21 MHz最大运行速度. |
| 英文摘要: |
| Using FPGA digital signal processing systems,it always busy with IEEE 754 floating-point to BCD code conversion.Based on the FPGA design,the paper presents a simple shift,addition,subtraction operations as the core of the transformation algorithm,for a state machine strueture with VHDL language,and achieved the use of 732 logic cells and the maximum operating speed of 69.21 MHz in EPEC6Q240C8. |
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